Â· Experience on Synthesis, interfacing with RTL and implementation designers to achieve better quality of results.
Â· Experience on Floorplan design, including placement of hard-macros, padring, power grid and custom analog routes.
Â· Experience on Static Timing Analysis related activities (constraints development, parasitic extractions, sign-off requirements).
Â· Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing).
Â· Hands-on experience with FinFET technologies is an advantage