Up to $250,000 a year
– Define overall verification strategies, methodologies, and simulation environment.
– Work with RTL designers, system architects, and block level verification engineers to develop top-level verification requirements and test plans based on specifications. Develop, maintain and publish verification specifications.
– Analyze and debug simulation failures
– Generates code coverage and functional coverage report
– Run gate level simulation and debug them.
-Perform the Constraint Random and Low power Verification, Develop System Verilog Assertions(SVA).
Requirements Skills/Experience:
-Minimum of 7-10 year experience in ASIC Verification.
– Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
– Fluent in verification languages such as UVM/OVM/RVM/System Verilog, Vera, Verilog
– Experience in writing Test-plans, creating directed and random test cases and low power simulations.
Should be adept at System Verilog assertions and coverage.
-Strong scripting skills in Perl, Python, shell etc.
– Strong problem-solving and debug skills to quickly identify and provide solutions under tight schedule pressure
Education: – B.S. with extensive industry experience
Job Type: Full-time
Salary: Up to $250,000.00 per year
Benefits:
Schedule:
Supplemental Pay:
Work Location: Remote
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