Envision what you could do here. At Apple, we believe new ideas and insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what you could accomplish. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight, and inspire millions of Apple’s customers every single day. SEG Packaging is a key part of the HW Technology team, located in Cupertino, CA. This team invents, designs, develops and integrates electronic packaging solutions for the Apple’s internal and customized external components of hardware for its consumer electronic products. As a NAND packaging engineer, you will lead the memory package development by managing the external memory vendors and steering their packaging design compatibility to Apple system components. You will partner with the internal SEG teams, defining the memory package architecture, die pad layout, package form factor, interconnect and package density, and will support the system and product teams and overall program through the development and NPI cycle.
4+ years experience in package design and assembly process development for stacked-die memory packages
Strong knowledge of wirebond and flip-chip assembly process applied to thin-die stacking
Strong knowledge of packaging materials, substrate technology, and their mechanical and thermal behaviors
Solid working experience in package test and reliability, system-level downstream process interaction, and packaging inspection metrology
Excellent engineering problem solving skills, with strong engineering physics and data driven analysis
Strong written and verbal communication skills
Define the memory package POR (plan of record): Package architecture, technology, process, form factor, layout, bill of materials (BOM), design rules, thermo-mechanical, signal integrity, power integrity Publish internal package specs for customized memory Establish trusting and collaborative relationships and communication channels, directly interfacing with vendors for memory package development and qualification Review, drive, and approve memory vendor DOEs, characterization plans, technology qualification Drive industry with advanced package design rules, processes, materials, and leading-edge specifications About 10% international travel required
Education & Experience
Ph.D. preferred or MSc (EE, ChemE, ME, Materials Science/Engineering major) with experience in package integration.